1. Field
This disclosure relates generally to semiconductors, and more specifically, to a process for manufacturing a semiconductor data storage device.
2. Related Art
Silicon nanodots or nanoclusters have been proposed for use in semiconductors to form nonvolatile memory devices. Additionally, others have taught the use of silicon nanoclusters in nonvolatile memory devices that store two bits of information per memory cell where a memory cell is implemented as a single transistor. In one approach a single continuous layer of silicon nanoclusters is used to store two bits because the nanocrystals are not electrically continuous. Charge is placed and stored at opposite ends of the single continuous layer in a memory transistor to implement the two stored bits of information and no charge is present in the middle of the continuous layer. However, random fluctuations in any of the silicon nanocluster size or the nanocluster density (i.e. nanocluster spacing) can result in lateral charge transport within the continuous nanocluster layer. The lateral charge transport results in disturbed data bits and unreliable data storage.
An alternative implementation of a nanocluster memory device that stores two data bits per device uses a discontinuous layer of nanoclusters to avoid the lateral charge transport described above. However, the known methods of making a two-bit per memory cell device with nanoclusters being present only near the source and the drain region of the device typically require additional semiconductor masking steps to manufacture and are thus more costly to implement. The additional masking step(s) is required to remove nanoclusters from the center of the memory device. Additionally, such devices are laterally larger in size. Further, some known devices with separated storage regions of nanoclusters are limited in the thickness of the gate dielectric in the center of the memory device. Thus, such devices are limited in the amount of voltage that may be applied to the devices. The voltage limitation is problematic as typically erase voltages must be high for such devices and the erase voltage value may damage or rupture the thin gate dielectrics.